Semiconductor Engineering

Facilitating Complex SoC Design Through Automation And Integration

The boundaries between IP reuse, interconnect design, and hardware-software integration are no longer independent.
Forbes

Cadence Brings Big Data And AI Analytics To SoC Verification

Forbes contributors publish independent expert analyses and insights. I write about disruptive companies, technologies and usage models. Over the years, the cost of designing a system on chip (SoC) ...
Nasdaq

Cadence Advances Hyperscale SoC Design with Expanded IP Portfolio for TSMC N3E Process Featuring Next-Generation 224G-LR SerDes IP

Proven interface IP architectures realized significant gains in performance and power efficiency on the TSMC N3E process 224G-LR SerDes PHY IP on the TSMC N3E process has achieved first-pass silicon ...
Embedded

Four key features every automotive SoC design needs

Vehicles can do much more than they were capable of a decade ago. Today’s modern connected vehicles have many convenient capabilities, from lane departure warnings to automated braking and ...
SDxCentral

Synopsys 5G SoC enhances 5G development with new RF design flow for TSMC N6RF process

RFICs (Radio Frequency Integrated Circuits) for wireless data transmission systems, such as transceivers and RF front-end components, are becoming more complex based on the demands of our connected ...
Semiconductor Engineering

Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools

Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and ...
Business Wire

Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach SerDes IP on TSMC’s N4P Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process for hyperscale ASICs, artificial ...
Electronic Design

Speeding the Process of Building IPs, Chiplets, and SoCs

How IP-XACT enables tool interoperability, multi-level abstraction, and accurate hardware/software interface alignment through structured metadata. Why integration automation is critical as complexity ...
EDN

Speeding AI SoC development with NoC-enabled tiling

Employing network-on-chip (NoC) technology in system-on-chip (SoC) designs has been proven to reduce routing congestion and lower power consumption. Now, a new NoC-enabled tiling methodology helps ...
TechSpot

Samsung taps AI to design first 3nm mobile processor with Synopsys

Why it matters: Samsung has rolled out its inaugural mobile system-on-chip built using cutting-edge 3nm process technology featuring gate-all-around transistors. But that's not even the most ...
Business Wire

Intel Foundry and Arm Announce Multigeneration Collaboration on Leading-Edge SoC Design

SANTA CLARA, Calif. & CAMBRIDGE, England--(BUSINESS WIRE)--Intel Foundry Services (IFS) and Arm today announced a multigeneration agreement to enable chip designers to build low-power compute ...
EDN

Getting started in structured assembly in complex SoC designs

The integration level of a system-on-chip (SoC) is defined in RTL, just like the rest of the design. Historically, RTL has been built through text editors. However, a decade or more ago, the sheer ...