EDN

Overcoming Static Timing Issues in Low-Power 3G Chips

Designers are using every design trick to reduce power in a 3G chip design. But, while cutting power, these tricks can create static timing analysis problems. Here's a look at how designers can close ...
Design-Reuse

Optimizing Floorplan for STA and Timing improvement in VLSI Design Flow

Static timing analysis is a technique of computing of cell delay and interconnect delay in design (known as path delay) and comparing it against constrain (timing specific) set in SDC file. This paper ...
Design-Reuse

IP Verification : Verifying timing of external IP key to SoC success

External intellectual property spans a broad range of technology. It can be as complex as an embedded digital signal processing (DSP) core or as primitive as a RAM instance. IP can come from an ...
Hot Rod

Setting Timing Curves

Ignition timing is an often-misunderstood concept that has a big effect on performance. An air/fuel mixture burn rate doesn't increase in direct proportion to engine rpm. Therefore, the faster the ...
Electronic Design

Oh, The Pain (Of Timing Closure At 28 nm)

What to do, what to do? Chip complexity continues to grow and design schedules are more aggressive, yet design teams are staying the same size or even being scaled back. Something has to give. A key ...
Electronic Design

Using Timing Constraints For Generating At-Speed Test Patterns

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...
EDN

Overcoming Static Timing Issues in Low-Power 3G Chips

The power issues encountered by today's mobile phone manufacturers is well documented. With cameras, web browsers, and other processing-intensive tasks entering next-generation phones, designers try ...