Semiconductor Engineering

Paradigms Of Large Language Model Applications In Functional Verification

This paper presents a comprehensive literature review for applying large language models (LLM) in multiple aspects of functional verification. Despite the promising advancements offered by this new ...
EDN

Functional verification tool adds X-Robust

The Ascent early functional verification solution for ASIC and FPGA designs now includes the first commercially available automated solution to ensure X-robust designs. Explicit and implicit X sources ...
The Next Platform

Reduce Manual Effort, Achieve Better Coverage With AI And Formal Techniques

PARTNER CONTENT Given the size and complexity of modern semiconductor designs, functional verification has become a dominant phase in the development cycle. Coverage lies at the very heart of this ...

Breker Verification Systems and Moores Lab AI Partner to Create First AI-Driven SoC Verification Solution

Test Suite Synthesis, agentic AI integration will enable automated specification test generation across range of SoC designs on varied ...

Breker Verification Systems Adds RISC-V Industry Expert Larry Lapides to its Advisory Board

Brings Advocacy for the adoption of RISC-V processors and processor verification tool standardsLeverages broad experience in EDA business ...
EDN

Reducing manual effort in coverage closure using CCF commands

Ensuring the reliability and performance of complex digital systems has two fundamental aspects: functional verification and digital design. Digital Design predominantly focuses on the architecture of ...